A technology called a scan test is conventionally known for testing an integrated semiconductor circuit. For example, in the scan test, a flip-flop is replaced by a scan flip-flop at the time of design of the integrated semiconductor circuit. In the scan test, at the time of a test mode, a shift register is formed by serially connecting the scan flip-flops within the integrated semiconductor circuit and a path is disposed in which the scan flip-flops are controllable or observable from an external input/output terminal.
Conventionally, a technology called a test point insertion (TPI) is known that inserts a mechanism to observe or control the value of a certain signal line in the integrated semiconductor circuit, to improve fault detection accuracy at the time of testing of the integrated semiconductor circuit.
For example, among TPI technologies, a technology is known that improves the fault detection accuracy by connecting a control circuit that includes the scan flip-flop to the signal line whose signal value is difficult to control, making the signal value controllable by the control circuit. For examples of such technologies, refer to Japanese Laid-Open Patent Publication Nos. 2006-84427, 2001-312529, and 2009-205414.
Conventionally, however, a control circuit capable of fixing the value of the signal line to be a specific value cannot cause the value of the signal line to transition from 0 to 1 or from 1 to 0. On the other hand, conventionally, a control circuit capable of causing the value of the signal line to transition from 0 to 1 or from 1 to 0 cannot fix the value of the signal line to be a specific value. For this reason, it is possible that a delay fault cannot be detected by use of either control circuit, resulting in a problem that the fault detection accuracy decreases.